John OConnor
San Diego Silicon, Inc.
16767 Bernardo Center Drive
Suite #27812
San Diego, CA 92198
858-376-7236
joconnor@sandiegosilicon.com
SPECIALIZATION
Design Consultant
Wireless Power Implantable Medical Device, Discrete Power Amplifier, NFC, BlueTooth LE and EMC.
Taught Practical RFIC CMOS Design at UFRGS Brazil 4 months 2009
Designed Digitally Controlled Baseband Filters, Attenuators, and OP Amps for Point to Point Microwave System
Designed Analog Feedback Control System for Wireless System
Designed 802.16 WIMAX SiGe wireless transceiver (VCOs, BB Filters, Successive Detection Loggers SDL-RSSI).
Many RF & Mixed Signal IC design & troubleshooting CMOS & BiCMOS IC�s.
Design / Debug Transceiver VCO/Synthesizer IC
Resolved IC Substrate Modeling Issues
Design Porting Between Semiconductor Manufacturers
Designed / Debugged Electric Vehicle Charger
Hands on design concept & prototype development of a RF & Mixed Signal CMOS Multi-mode GSM/WLAN/GPS transceiver IC�s
Management Consultant
Ran IC Engineering at a Multi-Mode Wireless Startup. Managed the company through the diligence phase to a liquidity event in January 2008.
Ran Engineering at a CMOS Multi-Mode Radio Startup. Focused on; Managed & motivated a team where the founders left very abruptly. The CEO and I took this company to liquidity event in August 2005.
Reviewed Companies Wireless Operations and Assessed Production Readiness.
Technical Diligence of Startup Companies and their Teams.
EXPERIENCE
San Diego Silicon, Inc.
San Diego, CA
September 2003 to Present
Design & Management Consultant
Ditrans Corporation,
Irvine, CA
A Digital Radio Company Funded By USVP May 2002 to Ditrans ceased operations September 2003
Vice President Design Engineering Responsible for all aspects of a CDMA receiver development. Managed a team of 28 engineers consisting of System Design, RF & Mixed Signal IC Design, VLSI Design and SW/Test Integration The Company�s product is a dual band RF input to Digital I/Q outputs CMOS fully integrated Low-IF Receiver.
Key Accomplishments:
� Managed through funding adversity that required reducing the engineering department by 40% to extend the company�s life. Reorganized my team to be able to produce an incredible receiver product.
� Implemented design/verification methodology that identified key performance limitations and corrected them to meet specifications.
� Demonstrated a 2GHz highly over sampled A/D Delta-Sigma dynamic range performance of 82 dB (CDMA Bandwidth).
� Demonstrated a best in class image rejection calibration scheme. Image rejection was better than 80 dB.
Ivera Systems (Co-Founded an optical networking semiconductor startup), San Diego CA 40 GB/s Ethernet product March 2001 to May 2002
Conexant Systems Inc.
, San Diego, CA (Spinout of Rockwell Semiconductor Systems) Digital Infotainment Division. September 1998 to March 2001 Division Director of IC Design Engineering managed a group of 55+ IC designers that consisted of RFIC, Mixed Signal IC, Digital VLSI and IC layout. Types of products included Satellite Demodulator Chipsets, Cable Modem Chipset, Video Encoders/Decoders.
Rockwell Semiconductor
(Acquisition of the PCSI-Cirrus Logic semiconductor business.) Wireless Communications Division. January 1997 to September 1998 Manager RF & Mixed Signal IC Design working on PHS and Personal Digital Cellular (PDC) chipsets for Japan.
Pacific Communication Sciences Inc. (PCSI) - Cirrus Logic (Cirrus Logic acquired PCSI April 1994) January 1992 to January 1997 Manager and Senior Member of Technical Staff, Analog & RF ASIC Development group. Assignments included the design and design supervision of commercial high volume Analog/RF and mixed mode Integrated Circuits (IC�s) for use in the Japanese Personal Handy Phone System (PHS) and other markets. PHS is a TDMA micro cellular portable phone using /4 DQPSK digital modulation. All IC were designed for low power operation, less than 2.7V.
Key Accomplishments:
� Brought custom integrated circuit design into PCSI, this required recruiting IC design and layout engineers, choosing CAD tools, and bringing up an Analog/RF debug capability.
� Managed and contributed to the design of PCSI�s 1st generation PHS. This was a 5 chip solution from base band to RF. My responsibility was the 4 analog/RF/mixed signal IC�s. This chipset was a cooperative effort between external resources and internal resources.
� Managed and contributed to the design of PCSI�s 2nd generation PHS. This chipset solution was designed completely internally. It went into production in Japan..
� Interviewed many design groups internationally and within the U.S.A to form partnerships/design centers. Technical portion of due diligence.
� Senior RF technical reviewer on the Mobile Data Base Station (MDBS) CDPD reviewing analog and RF discrete system and circuit design.
Northrop Corporation
Electronic Systems Group, Rolling Meadows, IL October 1984 to January 1992 As an Engineer Specialist in the Advanced Systems Technology Department my assignments included design and supervision of analog, RF circuits and systems from concept through prototype hardware development for R&D and production programs.
Key Accomplishments:
� A monolithic digitally controlled RF attenuator IC operating >1.5 Ghz with extremely low AM/PM. Designed in an 8 GHz Bipolar process.
� A monolithic RF switch combiner IC operating >3 Ghz. Designed in an 8 GHz Bipolar process.
� Other Integrated circuits include RF logging circuits, references, sample & holds, peak detectors, phase shifting networks, amplifiers, and mixers.
� Designed precision and broadband control loop circuitry, applications included automatic gain control (AGC), frequency locked loops (FLL�s), and phase locked loops (PLL�s).
� Completed design and tested R&D Monopulse RADAR simulator used for testing ECM.
Hughes Aircraft Company
Space & Communications Group, El Segundo, CA
June 1982 to October 1984
Member of technical staff Advanced Payloads Department. Assignments included R&D and flight programs requiring design and development of Analog, RF, and high-speed digital circuits.
Key Accomplishments:
� GaAs FET technology, simulated circuits, designed and tested a discrete version 1.6 Gbit/s digital elastic buffer and multiplexer design using a combination of ECL and GaAs FET components.
� Designed and tested discrete MIC RF circuits (operating from 20 Mhz to 1 GHz) i.e. envelope detector, buffer amplifier, VCXO, for a classified flight program.
� Completed design and antenna range tested an R&D S-band adaptive antenna system that included down conversion and signal processing (A/D, D/A, correlation, and signal conditioning). Co-authored two symposium papers on adaptive antennas.
EDUCATION
University Of Illinois, Urbana, IL B.S. Electronic Engineering May, 1982
Illinois Institute of Technology, Chicago, IL M.S. Electronic Engineering Program 50% Complete
ASSOCIATIONS
MISCELLANEOUS:
Dual Citizenship: USA, Ireland Senior Member of the Institute of Electrical and Electronic Engineers (IEEE).